1. Field of the Invention
The present invention relates to a highly-efficient multi-stage charge-pump circuit and a boosting method for the charge-pump circuit.
2. Description of Related Art
In recent years, a boosting circuit using a charge-pump circuit has been widely used as a high-side IPD (intelligent power device) equipped in an automobile. In order to generate a higher boosted voltage in a charge-pump circuit, the charge-pump circuit of the multi-stage configuration is required. FIG. 8 is a circuit diagram showing an existing, typical single-stage charge-pump circuit 800.
As shown in FIG. 8, the conventional single-stage charge-pump circuit 800 includes: a boosting clock driver 801 for receiving a clock signal OSC from an input terminal to drive a boosting capacitor 811; a first backflow preventative circuit 802 for applying a voltage corresponding to a power supply voltage VCC to the boosting capacitor 811 to prevent the backflow of charges; and a second backflow preventative circuit 803 for applying a boosted voltage to an output terminal OUT to prevent the backflow of charges in a like manner. The first backflow preventative circuit 802 and the second backflow preventative circuit 803 include N-channel metal oxide semiconductor field effect transistors (MOSFETs).
The boosting clock driver 801 includes a P-channel MOSFET 821 and N-channel MOSFET 822 series-connected between a power supply potential and a ground potential. Drain terminals of these two MOSFETs are connected together, and their gates are connected to the input terminal. The boosting clock driver 801 outputs a signal obtained by inverting an input signal from the output (V81). In other words, the boosting clock driver 801 functions as an inverter.
The first backflow preventative circuit 802 is connected between the power supply potential VCC and one end of the boosting capacitor 811. The other end of the boosting capacitor 811 is connected with the output (V81) of the boosting clock driver 801. The first backflow preventative circuit 802 has an N-channel MOSFET having connected gate and drain with the drain being connected with the power supply potential. The N-channel MOSFET of the first backflow preventative circuit 802 attains a so-called diode connection. Its source terminal is connected with the boosting capacitor 811, and a node therebetween is denoted by V82.
The second backflow preventative circuit 803 is connected between the node V82 and the output OUT. The second backflow preventative circuit 803 has an N-channel MOSFET. The N-channel MOSFET has connected gate and drain with the drain being connected with the node V82. Further, its source terminal is connected with the output OUT. The N-channel MOSFET of the second backflow preventative circuit 803 attains the diode connection. A capacitive load 813 is connected between the source and the ground potential, and a node therebetween is the output OUT. Further, a well terminal connected to a backgate of the N-channel MOSFET is connected with the power supply potential. Hence, a parasitic diode hardly operates to realize a stable operation of the entire circuit.
FIG. 9 is a timing chart of the existing, typical single-stage charge-pump circuit. As shown in FIG. 9, the clock signal OSC supplied from the input terminal is a time-varying signal that changes its level between the power supply potential VCC and the ground potential at a constant frequency. The clock signal OSC reaches a High level (e.g., power supply potential) at a timing t1, and the boosting clock driver 801 outputs a voltage of Low level (e.g., ground potential) from the output (V81). The boosting capacitor 811 is charged with the first backflow preventative circuit 802. Provided that a threshold voltage of the N-channel MOSFET of the first backflow preventative circuit 802 is represented by Vtn 801 (for example, 0.8 V), a voltage obtained at the node V82 at the timing t1 is expressed by Expression (1) below:V82=VCC−Vtn801  Expression (1)
After that, the clock signal OSC shifts to a LOW level at the timing t2, and a terminal of the boosting capacitor 811 on the boosting clock driver 801 side is at the power supply potential. At this time, charges corresponding to the voltage derived from Expression (1) above are accumulated in the boosting capacitor 811, so the voltage at the node V82 is derived from Expression (2):V82=2×VCC−Vtn801  Expression (2)
This voltage is higher than the power supply voltage. However, the first backflow preventative circuit 802 prevents charges from flowing back to the power supply potential side, so the charges of the boosting capacitor 811 are never discharged to the power supply potential. Further, this voltage is applied to the capacitive load 813 through the second backflow preventative circuit 803. Charges corresponding to this voltage are accumulated in the capacitive load 813. Provided that a threshold voltage of the N-channel MOSFET of the second backflow preventative circuit 803 is represented by Vtn 802 (for example, 1.9 V), a voltage VOUT at the output OUT is derived from Expression (3):VOUT=2×VCC−Vtn801−Vtn802  Expression (3)
Japanese unexamined patent publication No. H06-153493 discloses such a single-stage charge-pump circuit. The charge-pump circuit disclosed in this publication aims at saving power consumed by a limiter for stabilizing a boosted voltage.
FIG. 10 is a circuit diagram of an existing, typical two-stage charge-pump circuit 1000. As shown in FIG. 10, the existing two-stage charge-pump circuit 1000 includes a second boosting clock driver 1001, a second boosting capacitor 1011, and a third backflow preventative circuit 1002 in addition to components of the single-stage charge pump circuit 800 of FIG. 8. The same components as those of the single-stage charge pump circuit are denoted by like reference numerals, and their detailed description is omitted her. The second boosting clock driver 1001 has a gate connected with the output (V81) of the first boosting clock driver 801. The second boosting clock driver 1001 has a P-channel MOSFET 1021 and N-channel MOSFET 1022 series-connected between the power supply potential VCC and the ground potential. The second boosting clock driver 1001 outputs a signal from a node V101 at which drain terminals of these two MOSFETs are connected together. That is, the boosting clock driver 1001 functions as an inverter.
The third backflow preventative circuit 1002 is connected between the node V82 between the first boosting capacitor 811 and the first backflow preventative circuit 802, and the second backflow preventative circuit 803. The third backflow preventative circuit 1002 has an N-channel MOSFET. The N-channel MOSFET has connected gate and drain with the drain being connected with the node V82. Further, its source is connected with a drain of the N-channel MOSFET of the second backflow preventative circuit 803. That is, the N-channel MOSFET of the third backflow preventative circuit 1002 attains diode connection. A well terminal connected with a backgate of the N-channel MOSFET of the third backflow preventative circuit 1002 is connected with a power supply potential. Hence, a parasitic diode hardly operates to realize a stable operation of the entire circuit. Further, one end of the boosting capacitor 1011 is connected with the node V102 between the second backflow preventative circuit 803 and the third backflow preventative circuit. The other end of the boosting capacitor 1011 is connected with the output (V101) of the boosting clock driver 1001.
FIG. 11 is a timing chart of the existing two-stage charge-pump circuit 1000. As regards the operation of the two-stage charge-pump circuit, the voltage at the node V82 increases up to a level represented by Expression (1) above at the timing t1 similar to the operation of the foregoing single-stage charge-pump circuit. Next, at the timing t2, the voltage at the node V82 increases to a level represented by Expression (2) above similar to the operation of the foregoing single-stage charge-pump circuit. At this time, provided that a threshold voltage of the N-channel MOSFET of the third backflow preventative circuit 1002 is represented by Vtn 803 (for example, 1.9 V), a voltage that is calculated by replacing the threshold voltage Vtn 802 with the threshold voltage Vtn 803 is applied across the second boosting capacitor 1011. The same voltage is applied to the node V102. Next, at the timing t3, the first boosting clock driver 1001 outputs a voltage of High level from the output (V101). At this time, charges corresponding to the aforementioned voltage are accumulated in the second boosting capacitor 1011. Thus, the voltage at the node V102 is represented by Expression (4):V102=3×VCC−Vtn801−Vtn803  Expression (4)
This voltage is higher than the power supply voltage. However, since the first backflow preventative circuit 802 and the third backflow preventative circuit 803 prevent the charges from flowing back to the power supply potential side, the charges of the boosting capacitor 1011 are by no means discharged to the power supply potential. Further, this voltage is applied to the capacitive load 813 through the second backflow preventative circuit 803, and charges corresponding to the applied voltage are accumulated in the capacitive load. At this time, the voltage VOUT at the output OUT is derived from Expression (5):VOUT=3×VCC−Vtn801−Vtn802−Vtn803  Expression (5)
As mentioned above, in order to increase a boosted voltage, the following structure is generally adopted. That is, plural boosting capacitors are connected via the backflow preventative diodes between the power supply potential of the charge-pump circuit and the output terminal.
FIG. 12 is a graph showing a result of comparing a boosted voltage relative to the power supply voltage in a general single-stage charge-pump circuit with that in a general two-stage charge-pump circuit. As shown in FIG. 12, the boosted voltage is a voltage that is 1.4 to 1.6 times the power supply voltage with the single-stage one and is a voltage that is 1.8 to 2.1 times the power supply voltage with the two-stage one. In this case, the boosted voltage in the two-stage one is 1.3 times higher than that in the single-stage one. As mentioned above, the existing charge-pump circuit requires a multi-stage configuration for the purpose of obtaining a higher boosted voltage. Japanese unexamined patent publication No. 2000-123587 discloses a technique for providing such a multi-stage charge-pump circuit.
FIG. 13 is a schematic plan view of the layout of the single-stage charge-pump circuit. FIG. 14 is a schematic plan view of the layout of the two-stage charge-pump circuit. In these existing semiconductor devices, a large capacitive element composed of a MOS capacitor occupies the most of a semiconductor chip area. The two-stage one requires an area 1.7 to 1.8 times larger than that of the single-stage one.
However, in order to increase a boosted voltage, the existing charge-pump circuit needs to have the multi-stage configuration. The multi-stage boosting circuit has a problem in that a chip area increases in proportion to an increase in the number of capacitive elements, so a semiconductor chip costs high.